The number of cellular phone users all over the world is rapidly increasing and various new communication products supporting various new systems and services are being introduced. Currently, third-generation communication products based on CDMA 2000(Code Division Multiplex Access 2000) and W-CDMA(Wide-CDMA) technologies, and new information content and services, are being developed. In Europe, 2.5-generation GSM/GPRS products are well established. Third-generation communication systems need high-speed transmission, multimedia capabilities and compatibility with other communication systems. For example, a radio terminal requires dual mode operability and several communication protocol stacks in software. Before the invention of the stored program computer all software functions were implemented in single-function dedicated hardware. Software defined radio (SDR) technology enables a wireless terminal to support various kinds of wireless systems and services, such as second-and third-generation mobile systems (PDC*1,PHS, W-CDMA*2, GSM*3, etc.) and wireless LANs. By simply changing the software to reconfigure the terminal, users will be able to enjoy various wireless services in a seamless manner.
A communication system employs a digital signal processor (DSP) to reduce the signal processing load on a micro control unit (MCU). The DSP chip must be capable of boot-loading and needs a software program to perform any actual signal processing operation, the software program being downloaded from a memory device (e.g., a mass storage memory device) connected to the MCU and then being stored at an internal program memory thereof.
A semiconductor modem SOC (System On Chip) built into the radio terminal performs baseband signal processing, while the dual processor system (e.g., the MCU and the DSP) controls the operation of the overall system. The MCU handles the flow and control of the overall processing, while the DSP executes a specific signal processing based on the modem system in software or hardware. Thus, the radio terminal has a mass storage memory device and many hardware logics for a specific purpose, and such hardware logics are sometimes called Intellectual Property (IP). The modem SOC should be able to control a mixing signal device and a Radio Frequency (RF) device that are external to the modem SOC and an A/D converter, a D/A converter and a filter etc. that are built-in. Thus, the modem SOC has an interface RF Control circuit (IP) that is matched with an external device to be controlled.
For example, an RF control circuit (IP) is adapted to control an external RF device, the modem SOC reads/writes a control register of the external RF device by using the RF control IP. At this time, the MCU and the DSP should be able to access all the RF control circuit (IP) so as to share the one RF control circuit's function between two processors. Therefore, the respective buses used by the MCU and the DSP are connected to one RF control circuit (IP), and each processor has authority to access the RF control circuit (IP) through arbitration between respective accesses so as to alternately control the external RF device.
FIG. 1 is a block diagram showing an IP sharing device in a conventional system employing asynchronous dual processors.
Referring to FIG. 1, an arbiter 14 outputs a wait signal (WAIT) or a bus-grant signal (WAITNOT, being the logical complement of the WAIT signal) so that either the MCU 10 or the DSP 12 will communicate with the RF control circuit (IP) 26. If the arbiter 14 grants the bus access to the MCU 10, the arbiter 14 outputs a control signal (SELECT) so that the first through third MUXs (20, 22, 24) respectively select the address (Addr), the read/write strobe signal (nRW) and the data (Data) outputted from the MCU 10 through a first internal bus 16. If the arbiter 14 grants the bus access to the DSP 12, the arbiter 14 outputs a control signal (e.g., SELECTNOT, being the logical complement of SELECT) so that the first through third MUXs (20, 22, 24) respectively select the address (Addr), the read/write strobe signal (nRW) and the data (Data) outputted from the DSP 12 through a second internal bus 18.
The MCU 10 handles the flow and control of overall processing and receives the internal bus grant signal (WAITNOT) from the arbiter 14 to activate first internal bus 16 and to send and receive an address (Addr), a read/write strobe signal(nRW) and read/write data signal (Data) so as to communicate with the RF control circuit (IP) 26. The DSP 12 receives an internal bus grant signal from the arbiter 14 to activate a second internal bus (18) and to send and receive an address (Addr), a read/write strobe signal (nRW), and read/write data signal (Data) so as to perform a specific processing task with the shared RF control circuit (IP) 26.
First, second, and third multiplexers (MUX) (20, 22, 24) respectively receive and selectively output the addresses (Addr), the read/write strobe signals (nRW) and the read/write data signal (Data) outputted from either the MCU 10 or the DSP 12 in response to a control signal (SELECT) from the arbiter 14. That is, the first , second, and third multiplexers (MUX) (20, 22, 24) individually output one set of the address (Addr), the read/write strobe signal (nRW) and the data signal (Data) outputted from either the MCU 10 or the DSP 12. The RF control circuit (IP) 26 receives and stores the address (Addr), the read/write strobe signal (nRW) and the data (Data) respectively outputted from the first, second and third MUXs (20, 22, 24), and receives and constantly divides a system clock signal (not shown) to output a serial clock signal (SCLK), serial data (SDATA) and a serial enable signal (SEN) to an external device 28.
The arbiter 14 receives the address (Addr) and the read/write strobe signal (nRW) from either the MCU 10 or the DSP 12, and outputs a bus grant signal (WAITNOT) by a predetermined priority. That is, when the arbiter 14 grants a bus access to the MCU 10 according to the predetermined priority, the arbiter 14 applies a wait signal (WAIT) to the DSP 12. Conversely, when granting the bus access to the DSP 12, the arbiter 14 applies the wait signal (WAIT) to the MCU 10.
When the wait signal (WAIT) is applied to the MCU 10 or to the DSP 12, the MCU 10 or the DSP 12 stops operating and goes into a stand-by state. Also, the MCU 10 or the DSP 12 to which the wait signal (WAIT) is not applied, accesses the internal bus (16 or 18 respectively), and communicates with the RF control circuit (IP) 26, sending and receiving the address (Addr), the read/write strobe signal (nRW), and the read/write data(Data). At this time, the RF control circuit (IP) 26 communicates with the external device 28, transmitting serial data SDATA, a serial enable signal SEN, and a serial clock signal SCLK to the external device 28.
However, in such a conventional asynchronous dual processor system, while any one processor (e.g., either MCU 10 or the DSP 12) accesses the RF control circuit (IP), if the other processor tries to access at the same time, the processor having the access must stop operating. If the serial clock signal SCLK, the serial data SDATA and the serial enable signal SEN (the serial links outputted to the external device 28) have a long operation time, the other processor must stop operating and stand by during the operation time of the one processor, which reduces the efficiency of the system.
Furthermore, the conventional asynchronous dual processor system employs many MUXs to select each one of many addresses (Addr), read/write strobe signals (nRW) and data (Data) through arbitration and then to respectively apply each of those signals to one RF control circuit (IP) 26, thus causing a complicated circuit configuration.